The Chinese Patent No. 201080067067.7 discloses a low voltage, low power memory, as shown in FIG. 1 to 3. The memory cell shows in the FIG. 1, device 1 is the selector of the MOS transistor, device 2 is the sensor of MOS transistor, and device 4 is an anti-fuse element.
The memory array in FIG. 2 consisting of four memory cells A, B, C and D. The voltages for programming and reading of cell A are listed in the Table I.
TABLE ICellV(WP)V(WS)V(BL)V(BR)ProgrammingA SW/SB5.5 V2.5 V  0 VFloatingB SWUB5.5 V2.5 V2.5 VFloatingC UW/SB2.5 V  0 V  0 VFloatingD UW/UB2.5 V  0 V2.5 VFloatingReadA SW/SB1.0 V  0 V  0 VV SensingB SW/UB1.0 V  0 VFloatingFloatingC UW/SB  0 V  0 V  0 VV SensingD UW/UB  0 V  0 VFloatingFloating
SW: Selected Word line,
SB: Selected Bit line,
UW: Unselected Word line,
UB: Unselected Bit line,
For the prior art memory array of FIG. 3, if Cell A with Row m and Column s has been programmed, and the sequent programming is for Cell B of Row m and Column t. During the programming of Cell B, a 5.5V voltage is on the line WPm, and a high voltage about 5.2V is at Grate gms, as well as the gate of Nms, since the anti-fuse element Cms of programmed Cell A is conductive. This high voltage may cause same damage of transistor Nms of Cell A, such as leakage, reducing of reliability, etc. Low reliable Nms would results to some problem for reading of Cell A through Sense Amplifier.